x86 Instruction Set Reference

CVTSS2SD

Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value

Opcode	Mnemonic	Description
`F3 0F 5A /r`	`CVTSS2SD xmm1, xmm2/m32`	Convert one single-precision floating-point value in xmm2/m32 to one double-precision floating-point value in xmm1.

Description
Converts a single-precision floating-point value in the source operand (second operand) to a double-precision floating-point value in the destination operand (first operand). The source operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register. When the source operand is an XMM register, the single-precision floating-point value is contained in the low doubleword of the register. The result is stored in the low quadword of the destination operand, and the high quadword is left unchanged.

Description

Converts a single-precision floating-point value in the source operand (second operand) to a double-precision floating-point value in the destination operand (first operand). The source operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register. When the source operand is an XMM register, the single-precision floating-point value is contained in the low doubleword of the register. The result is stored in the low quadword of the destination operand, and the high quadword is left unchanged.

Operation
Destination[0..63] = ConvertFloatToDouble(Source[0..31]); //Destination[64..127] remains unchanged

SIMD Floating-Point Exceptions
Invalid, Denormal.

Protected Mode Exceptions

`#GP(0)`	For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
`#GP(0)`	For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
`#SS(0)`	For an illegal address in the SS segment.
`#PF(fault-code)`	For a page fault.
`#NM`	If TS in CR0 is set.
`#XM`	If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.
`#UD`	If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.

Real-Address Mode Exceptions

`#GP(0)`	If any part of the operand lies outside the effective address space from 0 to FFFFH.
`#GP(0)`	If any part of the operand lies outside the effective address space from 0 to FFFFH.
`#NM`	If TS in CR0 is set.
`#XM`	If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.

Virtual-8086 Mode Exceptions

Same exceptions as in Real Address Mode

`#PF(fault-code)`	For a page fault.
`#PF(fault-code)`	For a page fault.

Instruction	Latency	Throughput	Execution Unit
`CPUID`	0F3n/0F2n/069n	0F3n/0F2n/069n	0F2n
`CVTSS2SD xmm, xmm`	9/8/2	2/2/2	?