x86 Instruction Set Reference
SYSENTER
Fast System Call
Opcode | Mnemonic | Description |
---|---|---|
0F 34 |
SYSENTER |
Fast call to privilege level 0 system procedures. |
Description | ||||||||
---|---|---|---|---|---|---|---|---|
Executes a fast call to a level 0 system procedure or routine. This instruction is a companion instruction to the SYSEXIT instruction. The SYSENTER instruction is optimized to provide the maximum performance for system calls from user code running at privilege level 3 to operating system or executive procedures running at privilege level 0. Prior to executing the SYSENTER instruction, software must specify the privilege level 0 code segment and code entry point, and the privilege level 0 stack segment and stack pointer by writing values into the following MSRs:
These MSRs can be read from and written to using the RDMSR and WRMSR instructions. The register addresses are listed in Table 4-3. These addresses are defined to remain fixed for future IA-32 processors.
When the SYSENTER instruction is executed, the processor does the following:
The processor does not save a return IP or other state information for the calling procedure. The SYSENTER instruction always transfers program control to a protected-mode code segment with a DPL of 0. The instruction requires that the following conditions are met by the operating system:
The SYSENTER can be invoked from all operating modes except real-address mode. The SYSENTER and SYSEXIT instructions are companion instructions, but they do not constitute a call/return pair. When executing a SYSENTER instruction, the processor does not save state information for the user code, and neither the SYSENTER nor the SYSEXIT instruction supports passing parameters on the stack. To use the SYSENTER and SYSEXIT instructions as companion instructions for transitions between privilege level 3 code and privilege level 0 operating system procedures, the following conventions must be followed:
The SYSENTER and SYSEXIT instructions were introduced into the IA-32 architecture in the Pentium II processor. The availability of these instructions on a processor is indicated with the SYSENTER/SYSEXIT present (SEP) feature flag returned to the EDX register by the CPUID instruction. An operating system that qualifies the SEP flag must also qualify the processor family and model to ensure that the SYSENTER/SYSEXIT instructions are actually present. For example: IF (CPUID SEP bit is set) THEN IF (Family = 6) AND (Model < 3) AND (Stepping < 3) THEN SYSENTER/SYSEXIT_Not_Supported FI; ELSE SYSENTER/SYSEXIT_Supported FI; When the CPUID instruction is executed on the Pentium Pro processor (model 1), the processor returns a the SEP flag as set, but does not support the SYSENTER/SYSEXIT instructions. |
Operation |
---|
if(CR0.PE == 0) Exception(GP(0)); if(SYSENTER_CS_MSR == 0) Exception(GP(0)); EFLAGS.VM = 0; //Insures protected mode execution EFLAGS.IF = 0; //Mask interrupts EFLAGS.RF = 0; CS.SEL = SYSENTER_CS_MSR; //Operating system provides CS //Set rest of CS to a fixed value CS.SEL.CPL = 0; CS.BASE = 0; (* Flat segment *) CS.LIMIT = 0xFFFF; //4 GByte limit CS.ARbyte.G = 1; //4 KByte granularity CS.ARbyte.S = 1; CS.ARbyte.TYPE = 0xB; //Execute + Read, Accessed CS.ARbyte.D = 1; //32-bit code segment CS.ARbyte.DPL = 0; CS.ARbyte.RPL = 0; CS.ARbyte.P = 1; SS.SEL = CS.SEL + 8; //Set rest of SS to a fixed value SS.BASE = 0; //Flat segment SS.LIMIT = FFFFH; //4 GByte limit SS.ARbyte.G = 1; //4 KByte granularity SS.ARbyte.S = 1; SS.ARbyte.TYPE = 3; //Read/Write, Accessed SS.ARbyte.D = 1; //32-bit stack segment SS.ARbyte.DPL = 0; SS.ARbyte.RPL = 0; SS.ARbyte.P = 1; ESP = SYSENTER_ESP_MSR; EIP = SYSENTER_EIP_MSR; |
Flags affected |
---|
VM, IF, RF (see Operation above) {exceptions protected} #GP(0) If SYSENTER_CS_MSR contains zero. |